In traditional circuit design tools, designers reduce power consumption of the design by recurring to techniques such as clock gating, power gating, memory gating, operand isolation, bus encoding, among others. However, designers have little insight as to the limits of power consumption reduction. Moreover, in current IC designs and activity charts, the floor of consumed power by a circuit is typically unknown. This may result in unnecessary attempts by a designer to apply lengthy and cumbersome techniques with little to no effect in consumed power reduction.
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